Error correction codes (ECC) are used in a variety of systems, including in data storage and communications. While older ECC decoder designs have a fixed processing latency, newer ECC designs, such as iterative low density parity check (LDPC) decoders, iterative Reed Solomon (RS) decoders, and other iterative ECC decoders, may have a variable latency which may cause a long delay. For example, one new system for processing received data has a RS decoder and an LDPC decoder. A straightforward way of processing data using this system would be to maintain sequencing in the data path. For example, data coming out has the same sector numbers or ordering as the data coming in. However, this straightforward data handling approach may have some drawbacks such as long latency and/or large memory requirements in the event there is a sector with a large amount of error and/or two sectors with large amounts of error are located very near each other in a sequence of sectors. It would be useful to develop some techniques for processing data which reduce memory requirements and/or latency.